The present invention concerns a low power RF receiver with redistribution of synchronisation tasks. The low power RF receiver includes in particular an antenna for receiving radio-frequency signals originating from satellites, a reception and shaping stage for the radio-frequency signals supplied by the antenna, a correlation stage formed of several channels which each include a correlator, said correlation stage receiving intermediate signals shaped by the reception stage, a microprocessor connected to the correlation stage and intended to calculate X, Y and Z position data, velocity and time data as a function of the data extracted, after correlation, from the radio-frequency signals transmitted by the satellites. In case of a GPS receiver, the data extracted from the GPS signals are, in particular, the GPS message and pseudo-ranges.
Currently, 24 satellites are placed in orbit at a distance close to 20,200 km above the surface of the Earth on 6 orbital planes each offset by 55° with respect to the equator. The time taken by a satellite to complete one entire rotation in orbit before returning to the same point above the Earth is approximately 12 hours. The distribution of the satellites in orbit allows a terrestrial GPS receiver to receive the GPS signals transmitted by at least four visible satellites to determine its position, its velocity and the local time for example.
For the transmission of the radio-frequency signals, each satellite includes an atomic clock set at a frequency of 10.23 MHz in order to supply precise time data to terrestrial GPS receivers. Terrestrial control stations allow certain satellite data to be corrected if necessary, for example as regards its time data and orbital data.
Each of these satellites transmits radio-frequency signals formed of a first carrier frequency L1 at 1.57542 Ghz on which are modulated the P-code at 10.23 MHz and the C/A PRN code at 1.023 MHz peculiar to each satellite with the GPS message at 50 Hz which contains the ephemerides and almanac data used in particular for calculating position, and a second carrier frequency L2 at 1.2276 Ghz on which are modulated the P-code at 10.23 MHz with the GPS message at 50 Hz. In civilian applications, only carrier frequency L1 with the C/A code is used by the terrestrial receivers for calculating the X, Y and Z position, velocity and time, in accordance with the GPS message.
The C/A PRN code (pseudo random noise) of each satellite, which is also called the Gold code, is a unique pseudo random code for each satellite so that the signals transmitted by the satellites can be differentiated within the receiver. All the Gold codes have the characteristic of being orthogonal, i.e. by correlating them with each other, the correlation result gives a value close to 0. This characteristic allows several radio-frequency signals originating from several satellites to be processed independently and simultaneously in several channels of the same GPS receiver.
This C/A code is a digital signal which is formed of 1023 chips and which is repeated every millisecond. This repetition period is also defined by the term epoch of the Gold code. It is to be noted that a chip takes values of 1 or 0 as for a bit. However, a chip (a term used in GPS technology) should be differentiated from a bit which is used to define a unit of information.
The Gold codes are defined for 32 satellite identification numbers which still leaves a free choice as to the specific code attributed to each other satellite which will be put in orbit on one of the orbital planes.
In the GPS receiver at the correlation stage, a C/A code generator generates a known replica of a C/A satellite code by a sequence of 1023 different chips for each phase adjustment for acquiring a satellite. The chip codes are offset in time in a shift register implementation by orienting the clock which controls said shift registers.
In several areas of activity, the use of GPS receivers which are portable or integrated in other devices of larger dimensions has enabled users to be provided with navigation data facilitating, in particular, the taking of bearings and knowledge of their location. One may cite in particular the use of GPS receivers incorporated in the instrument panel of road vehicles and in co-operation with cartographic data stored to allow a route to be indicated to a driver of said vehicle.
The reduction in size of GPS receivers has become a necessity to allow the incorporation thereof in objects which can easily be carried by a single person wishing to know his position and velocity at any location in a relatively precise manner. With the reduction in size of these receivers, which are powered by batteries, constructions guaranteeing a certain saving in the energy consumed by said receivers have had to be designed, hence the manufacturing of low power receivers.
Of course, the consumption requirements are dependent on the capacity of the supply battery to supply power to the GPS receiver when the received radio-frequency signals are processed. The smaller the battery, the more necessary it becomes to design smaller integrated circuit electronic units for the GPS receiver. Further the manner in which the signals are processed in said circuits to extract the GPS message and the pseudo-ranges from each satellite picked up have to be processed in an optimal manner.
Since mounting of GPS receivers in portable objects, such as cellular telephones or wristwatches, is envisaged, the integrated circuits must be designed so that their power consumption is not too large in order to avoid having to change the battery of the object too frequently or having to keep recharging an energy accumulator at frequent intervals.
In the case of an integration in a wristwatch, a reduction in size is imposed not only for the board carrying the integrated circuits for processing the received signals, but also for the antenna and the accumulator insofar as possible. A reduction in power consumption may be achieved by using a technology of reduced size for manufacturing the integrated circuits of the correlator and the calculation by micro-controller. CMOS technology of 0.5 μm may for example be used, or in the near future, with a CMOS technology of 0.18 μm while guaranteeing proper operation at a high frequency. Moreover, optimisation of the GPS signal processing algorithm of the microprocessor implemented in the correlator may further reduce the power consumption of the receiver.
Several embodiments of low power receivers have already been the subject of Patents for the purpose of saving, as far as possible, the energy consumed by the receiver during operation. U.S. Pat. No. 5,650,785 of the company Trimble Navigation Limited, may be cited, concerning a low power GPS receiver. This receiver includes, in particular, a RF section with frequency division and quantification of the GPS signals for the correlation stage, and a microcontroller device which controls a supply voltage modulator. This supply voltage modulator is used to deactivate the RF section for a period of time less than the time necessary to correlate the GPS signals in order to reduce as far as possible the power consumption of this heavy power consuming RF section while letting the correlation stage operate.
Given the significant data transfer which has to occur between the correlator and the microprocessor, in order to increase the signal processing speed while trying to save energy, the current tendency is to provide the receiver with a 32-bit microprocessor. However, improving the capacities of the receiver with such microprocessors has the drawback of a significant exchange of data between said microprocessor and the demodulator or correlator, this exchange moreover occurring at a frequency exceeding one kHz.
In order to fix an order of magnitude of the current energy consumption of low power GPS receivers, the GPS receiver called ACE III of Trimble Navigation Limited may be taken as an example. This receiver has an 8 channel architecture, this architecture being the quickest for the purpose of saving energy and guaranteeing better reliability. The dimension of the board with the components is 8.26 cm×4.65 cm ×1.15 cm. The power consumed is less than 0.5 W without taking account of the consumption of the antenna amplifier. This GPS receiver device is used for navigation, tracking (localisation), data collection or other applications in which the device is battery powered. This receiver includes 32 correlators.
A first integrated circuit is the RF/IF frequency converter intended to send the shaped data to the correlation stage, in which there is a passage to an intermediate frequency in order to reduce, amongst other things, the power consumption, without deteriorating the quality of the received signal. A second integrated circuit receiving the intermediate signals is the GPS DSP whose microprocessor is of the 32-bit type. The power consumed by this receiver is of the order of 0.5 W for a voltage not exceeding 3.5 V. Even with such a relatively low consumption, this receiver is hardly in a position to be able to be fitted for example to a watch or a portable telephone provided with a low power accumulator or a battery.
If a real time calculation is desired, this requires significant calculating power which can only be achieved by means of large microprocessors, in particular with 32-bit microprocessors.